This invention relates to a circuit for driving a liquid crystal display panel, and in particular, a circuit for driving an active matrix liquid crystal display panel having thin film transistor elements.
Active matrix liquid crystal display panels which include thin film transistor (TFT) elements have recently been improved to make them of practical use as a display panel for a pocket sized TV. The liquid crystal display devices are capable of receiving an input video signal and displaying the corresponding picture. The displayed picture was initially two inches across having two hundred and forty rows and two hundred and twenty columns. Driving systems such as the analog point at a time system and the analog line at a time system are adapted to these liquid crystal display devices to supply analog video signals directly to a liquid crystal display.
Reference is now made to FIG. 1 wherein a block diagram of a conventional analog line sequential system consisting of an X driver 1 and a Y driver 2 for driving an active matrix panel 3 is depicted. Panel 3 is divided into N rows and M columns X driver 1 includes a shift register 4 having M shift steps.
M sample hold circuit groups, generally indicated as 5, correspond to each M step of shift register 4, M being an integer. A second sample hold circuit group 6 includes M sample hold circuit groups corresponding to each M sample hold group of hold circuit group 5, thereby providing a two step sample hold circuit group. Each sample hold circuit of circuit group 5 includes an analog switch 7 which receives the M step output from shift register 4 and a VIDEO signal input at an input 60 and provides an output to a buffer amplifier 9. A capacitor 8 receives the output of analog switch 7 and holds the sample. The control terminal of each analog switch 7 is connected to the output of the respective steps of shift register 4. Each sample hold circuit of sample hold circuit group 6 includes an analog switch 10, a buffer amplifier 12 receiving an input from analog switch 10 and a capacitor 11 receiving an input from analog switch circuit 10 Capacitor 11 holds the input sample. The control terminal of each analog switch 10 is connected to input 63, which receives a latch clock signal LCL. The input terminals of the analog switch 10 are each connected to the output of the buffer amplifiers 9.
The outputs of buffer amplifiers 12 are each input at a source line 15 which is connected in the column direction to a column of active matrix liquid crystal panel 3. Shift register 4 receives a start pulse signal XSP at an input 61 for beginning the shifting of shift register 4 and a clock signal XCL at an input 62 for timing the shifting of shift register 4.
Y driver 2 includes a shift register 13 having N steps corresponding to N outputs, N being an integer. Shift register 13 receives a start pulse signal YSP at input 64 for beginning the shifting of shift register 13 and a clock signal YCL for timing the shifting of shift register 13. Each output of shift register 13 inputs into a respective buffer amplifier 14. The respective outputs of buffer amplifiers 14 are each input to active matrix liquid crystal panel 3 at a gate line 16 which is connected in the row direction to a row of active matrix liquid crystal panel 3.
Active matrix liquid crystal panel 3 may then be considered to be divided by M source lines 15 arranged in the column (vertical) directions and N gate lines 16 arranged in the row (horizontal) direction. A pixel transistor 17, positioned at the intersection of each source line 15 and gate line 16, receives as its gate input the signal from gate line 16 and as its data input a signal from source line 15. Each pixel transistor 17 is associated with an individual pixel electrode 18 and receives an output from pixel transistor 17. A common electrode 19 is opposing to pixel electrodes 18.
During one horizontal scanning period 1H, when one gate line 16 is selected, a start pulse XSP is input to X driver 1 causing each address of the shift register to be shifted in accordance with the input clock signal XCL. Upon the output signals of each respective step of shift register 4, the VIDEO signal level input at input 16 is latched by each sample holder group 5. Upon the completion of 1H, the latch pulses of latch clock signal LCL input at input 63 are supplied to respective analog switches 10 of the sample hold circuit 6 and are latched as a group in sample hold circuit group 6. During the next scanning period 1H the latched VIDEO signal is input to liquid crystal panel 3 to effect display Then, the sample hold circuit of sample hold circuit group 5 inputs the video signal for the next gate line 16.
This arrangement is less than satisfactory particularly when utilized for a gray scale display having high resolution and comparatively less bits of input data. Several problems occur particularly in the prior art constructions utilize digital data stored in a video RAM (VRAM) which is displayed through a digital data process.
When a liquid crystal display panel having a larger display size, such as five to fourteen inches, is utilized it becomes necessary to increase the number of pixel elements. When a liquid crystal display panel having N pixel elements per column and M pixel elements per row is utilized for displaying the picture at a refresh frequency F.sub.r, one horizontal scanning period T.sub.1H (hereinafter referred to as 1H) may be expressed by the following formula: EQU T.sub.1H =1/(N.times.f.sub.R) sec.
Therefore, when all of the X drivers are connected in cascade and the data is sampled by a single clock the clock frequency f.sub.CL is expressed by the following formula: ##EQU1## For example, when M equals 1,000, N equals 1,000 and the refresh frequency f.sub.R equals 100 Hz, the clock frequency f.sub.CL is expressed by the formula: EQU f.sub.CL =100MHz
However, it is difficult to obtain a supply of integrated chip drivers which can be operated at such a high speed.
To overcome these problems, divided X drivers have been constructed to input the data in parallel thereby avoiding the construction having all of the X drivers connected in cascade. The X driver is divided into k sections, k being an integer. Accordingly, to input data in each of the X drivers in parallel the sampling frequency of the X drivers becomes f.sub.CL/k, thereby decreasing the necessity for high speed operation.
Reference is now made to FIG. 2, wherein a block diagram depicting a parallel input system having two analog line sequential drivers is shown. The display data is input digitally from VRAM1 to digital to analog converter 20a. Digital to analog converter 20a outputs analog video signals VIDEO L. Divided analog line sequential driver 1a receives video signal VIDEO L and provides an output to drive a panel portion 3a of active matrix panel 3. Similarly, digital to analog converter 20b converts the digital data received from VRAM 2 to analog signal VIDEO R. An analog line sequential driver 1b receives the VIDEO R signal and provides a driving signal to matrix panel 3b of active matrix panel 3. Y driver 2 is connected to liquid crystal panel 3. The other necessary and conventional clock signals are also input to the drivers as discussed above, but are not shown.
This parallel input system has also been less than satisfactory. This construction requires operating digital analog converters 20a, 20b at a high speed. Additionally, when an offset voltage is generated between the analog output of digital to analog converters 20a, 20b, the contrast ratio of the left half matrix panel 3a is different from that of right half matrix panel 3b. Additionally, a vertical line may be generated at the boundary of left panel 3a and right panel 3b.
Another conventional circuit for driving a liquid crystal display panel consists of digital input terminals of K bits and an external power supply at a level of 2.sup.k. One of the external power supplies corresponding to the data is selected. If the number of source lines is M, M being an integer, the number of analog switches for driving the circuit becomes large, namely M.times.2. As a result, it becomes difficult to put such a circuit into practical use because of chip size and cost.
Accordingly, it is desirable to provide a circuit for driving an active matrix liquid crystal display panel which overcomes these shortcomings of the prior art devices and produces an analog gray scale display from a large volume of digital data.